Method of realigning the local oscillators of a receiver and device for implementing the method

ABSTRACT

The present invention relates to a method of realigning the local oscillators of a receiver, as well as a device for implementing the method. In a receiver with a high frequency/intermediate frequency translation oscillator, an intermediate frequency/baseband translation oscillator, and a sampling oscillator receiving a signal modulated by at least one circuit for inverse fast Fourier transform FFT -1  computation according to a multicarrier modulation of OFDM (Orthogonal Frequency Division Multiplexing) type with addition of a transition interval at the start of each transmission interval. The spectrum of the signal has two master lines with a fixed frequency difference between them. The method is characterized by the following steps: (1) determination of the start of a transmission interval; (2) determination of the position of the two master lines; and (3) computation of the variation of the phases of these two lines as a function of time, and exploitation of the result to set the frequency of the sampling oscillator and of the intermediate frequency baseband translation oscillator. The invention will find particular application to digital television.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the realigning of the local oscillatorsof a receiver making it possible to receive a signal modulated by atleast one circuit for inverse fast Fourier Transform computationaccording to a multicarrier modulation of OFDM (Orthogonal FrequencyDivision Multiplexing) type.

2. Description of the Related Art

In the International Patent Application PCT/FR 89/00546 filed in thename of THOMSON-CSF, there is described a method for transmittingmodulated waves using a plurality of frequencies simultaneously,comprising successive steps of transmission of symbols for a durationT+ΔT, two transmission frequencies being 1/T apart, T being the usefultransmission interval and ΔT being the transition interval. In the abovepatent application, there is also described a transmitter and a receiverenabling this method to be implemented by using, in the transmitter, acircuit for inverse fast Fourier transform (FFT⁻¹) computation in orderto carry out the modulation of the signal and, in the receiver, acircuit for fast Fourier Transform (FFT) computation in order to carryout the demodulation of the signal received. Furthermore, to enable thereceiver to be synchronised with the transmitter, the spectrum of themodulated signal comprises two master lines having a fixed frequencydifference between them. By using these two master lines, it is possibleto slave the local oscillators as well as the sampling clock of thereceiver. In the patent application mentioned above, there is thereforedescribed a device for analog feedback control using the two masterlines to control certain local oscillators of the receiver as well asthe clock giving the sampling frequency.

As shown in FIG. 1, the feedback control device making it possible torealign the local oscillators of the receiver described in theabove-mentioned patent application, comprises essentially a band-passfilter 2, a band-pass filter 3, a mixer 4 and a phase-lock loop (PLL) 1generating a reference frequency for three other PLLS. The two filters 2and 3 are connected in parallel and receive, among other things, atinput two frequencies f_(A), f_(B), arising from the circuit fortranslating Intermediate Frequency into Baseband, as is explained in theabove application. The outputs from the two band-pass filters 2 and 3are sent to the mixer 4. The output f rom the mixer 4 is input to thephase-lock loop 1. This phase-lock loop comprises a mixer 5 whose outputis connected to the input of a low-pass filter 6. The output of thelow-pass filter 6 is connected to a voltage-controlled oscillator (VCO)7. The output of the oscillator 7 is connected to the input of thephase-lock loop, namely on the other input of the mixer 5. The outputfrom the phase-lock loop 1 is also input to three phase-lock loops 8, 9,10. These phase-lock loops are frequency-division phase-lock loops. Thephase-lock loops 8, 9, 10 constitute the outputs of the feedback controldevice and deliver frequency references to the various localoscillators, namely the local oscillator of the highfrequency/intermediate frequency f'_(HF) translation circuit, thesampling clock f_(e), local oscillator of the Intermediate Frequency tobaseband f'_(i) translation circuit.

The circuit described above operates as follows. The filter 2 selectsthe frequency f_(A) namely the frequency of one of the two master linestransmitted by the transmitter. The filter 3 selects the frequency f_(B)namely the frequency of the other master line. The mixer 4 performs thebeating between the frequencies f_(A) and f_(B). The phase-lock loop 1delivers the value of the differences between frequencies f_(A) andf_(B). The difference between the frequencies f_(A) and f_(B) ontransmission, determined by the transmission standard, is known.Comparison on reception enables a frequency reference and phasereference to be delivered. The phase-lock loops 8, 9 and 10 thereforedeliver frequency and phase references to the various local oscillatorsand to the sampling clock which are used in the receiver.

SUMMARY OF THE INVENTION

The object of the present invention is to propose a new method ofrealigning the local oscillators of the receiver allowing entirelydigital operation, as well as a device f or implementing the method.

This new method and new device make it possible to lower the complexityof the clock recovery system at the level of the receiver, thusdecreasing its cost.

The subject of the present invention is a method of realigning theoscillators of a receiver comprising a high frequency/intermediatefrequency translation oscillator, an intermediate frequency/basebandtranslation oscillator, and a sampling oscillator receiving a signalmodulated by at least one circuit for inverse fast Fourier transform(FFT⁻¹) computation according to a multicarrier modulation of OFDM(Orthogonal Frequency Division Multiplexing) type, the spectrum of thesaid signal comprising two master lines having a fixed frequencydifference between them, the method being characterised by thecomputation of the variation of the phases of the two lines as afunction of time with the aid of a fast Fourier Transform on reception,the said oscillators being frequency adjustable and the result of thesaid computation serving to set the frequency of the sampling oscillatorand the frequency of at least one of the other two oscillators.

Other characteristics and advantages of the present invention willemerge on reading the description given hereafter of a preferredembodiment of a device implementing the present invention, thisdescription being given with reference to the attached drawings inwhich:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 already described is a block diagram of an embodiment of afeedback control device making it possible to realign the localoscillators of a receiver according to the prior art;

FIG. 2 is a block diagram of an embodiment of a receiver in which thepresent invention can be implemented;

FIG. 3 is a diagram explaining the implementation of the method of thepresent invention, and

FIG. 4 is another diagram explaining the implementation of the method ofthe present invention.

To simplify the description, in the figures the same references havebeen used to designate the same elements.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The method of realigning the local oscillators according to the presentinvention can be implemented in a receiver such as represented in FIG.2. This receiver therefore comprises, in manner known per se, areception antenna 20, a receiver circuit 21 principally transforming thereception frequency into an intermediate frequency, a translationcircuit 22 transforming the intermediate frequency into a basebandfrequency, an analog digital converter 23, a packet synchronisingcircuit 24, a demodulating circuit 25 consisting of a fast Fouriertransform circuit, a feedback control circuit 26, an analysis circuit27, a correction circuit 28, a decision circuit 29 and an exploitationcircuit 30. These various circuits as well as their operation have beendescribed in the International Patent Application PCT/FR 89/00546. Morespecifically, the receiver 21 comprises an amplifier 210 amplifying thesignal arising from the antenna 20. The output of the amplifier 210 isconnected up to the first input of a mixer 214 whose other inputreceives a frequency arising from a local oscillator 213. The output ofthe mixer 212 is connected up to the input of a band-pass filter 214.The output of the band-pass filter 214 is connected up to the input ofan amplifier 215 which comprises a loop for negative-feedback with anautomatic gain-control circuit 216. In this circuit, the amplifier 210amplifies the signal picked up by the antenna 20. By beating with ahigh-frequency signal delivered by the local oscillator 213, the mixer212 lowers the frequency of the signal received. The signal at theoutput of the mixer is filtered by the filter 214, which makes itpossible to eliminate the signals which are foreign to the signals whichit is wished to be able to receive. the amplifier 215 under control ofthe automatic gain circuit 216 carries out the amplification of theintermediate frequency signal f'_(i) obtained at the output of thecircuit 21. This intermediate frequency signal is therefore sent to anintermediate frequency to baseband translation circuit 22 comprising, asrepresented in FIG. 2, a mixer 220 which receives the amplifiedintermediate frequency on one input and the frequency arising from alocal oscillator 222 on the other input. The output from the mixer issent to a low-pass filter 221. In this case, the mixer 220 performsbeatings between the signal delivered by the oscillator 222 and thesignals with the intermediate frequency f'_(i) and supplies a basebandsignal. The filter 221 selects the desired part of the spectrum so as toobtain a baseband signal sent to the analog digital converter 23. Theconverter therefore performs a digital sampling of the signal at thesampling frequency f'_(e) synchronised by the feedback control device26. The packet-synchronisation circuit 24 makes it possible among otherthings to determine the start of a transmission interval, which enablesthe carriers to be reorthogonalised. This type of operation allows arough packet synchronisation (to within a few samples). A finersynchronisation is carried out by the analysis circuit 27 by examiningthe rotation of the phase throughout the band. The packet-synchronisingcircuit comprises, for example, means of subtracting the signal with asignal delayed by a duration T. As long as the two samples are handledin the same transmission interval of duration T+ΔT, their difference isnearly constant. This is true for each transmission interval over aduration ΔT decreased by the time of arrival of the most distantmultiple echo. By contrast, rapid fluctuation of this differenceindicates that the two samples no longer belong to the same transmissioninterval. Thus, from the difference of the two samples, the instant ofchange of transmission interval is determined and thereby asynchronisation of the intervals of transmission calledpacket-synchronisation. This device for packet-synchronisation operatesat the sampling frequency f'_(e). Furthermore, in the embodimentrepresented, the demodulating circuit 25 consists of a circuit for fastFourier transform computation. The receiver described above is adaptedto receive signals modulated in a transmitter comprising at least onecircuit for inverse fast Fourier transform computation. The modulationis a multicarrier modulation of OFDM (Orthogonal Frequency DivisionMultiplexing) type with addition of a transition interval Δt at thestart of each transmission interval t, the spectrum of the said signalcomprising two master lines K1 and K2 having a fixed frequencydifference between them.

The mathematical elements enabling the method of the present inventionto be implemented will be given hereafter. These mathematical elementsare given by starting from the following assumptions. For thetransmitter:

the number of channels is 512;

the signal is composed, in this case, of 2048 points, for a transmissionsampling frequency twice the Shannon frequency;

the transition interval then corresponds to 256 samples.

In this case, the signal transmitted by the transmitter is given by theequation below: ##EQU1## where Δ=q×2T_(e) π(t)=1 0≦t≦Δ(with q=1152, i.e.1024+128 in the present case) T_(e) =1/f_(e) π(t)=0 elsewhere N=2048 D:offset of the carriers in the transmitted spectrum, ρ_(j),k φ_(j),k isthe item of information transported by the k^(th) carrier during thetime interval [jΔ, (j+1)Δ] in which f_(e) corresponds to the samplingfrequency and Δ to the interval of transmission consisting of the usefulpart plus the transition interval.

In a manner known per se, the signal S(t) undergoes, on transmission andon reception, a certain number of translations, namely, on transmission,a baseband to intermediate frequency f_(i) translation and anintermediate frequency/high frequency translation giving the frequencyf_(HF) and, on reception, a high frequency f'_(HF) to intermediatefrequency f'_(i) translation and an intermediate frequency f'_(i) tobaseband translation. After translation, namely at the input of theanalog digital converter 23, we receive the signal represented by theequation: ##EQU2## with f_(i) : intermediate frequency of transmission

f'_(i) : intermediate frequency of reception

f^(R) _(i) : intermediate frequency of theoretical reception, ##STR1##f_(HF) : HF frequency of transmission f'_(HF) : HF frequency ofreception.

We put: ##EQU3## and it follows that ##EQU4## We sample at the frequency##EQU5## (in the above equations δ₁, δ₂, δ₃ represent the frequencyoffsets for which it is sought to compensate).

At the output of the analog digital converter 23, we obtain the signalrepresented by the formula: ##EQU6## we take the standpoint of a samplen corresponding to a start of transmitted packet, for example thej^(th). We must have ##EQU7##

In this case, we recover the information transmitted in respect to blockNo. j and by numbering the samples from 0 to 1151 starting from n weobtain: ##EQU8##

We have: ##EQU9## and we put ##EQU10##

Then ##EQU11##

We put: ##EQU12## Then: ##EQU13##

We shift by 128 samples, i.e.: ##EQU14##

The demodulation by the circuit for fast Fourier transform computationgives: ##EQU15## ρ representing the amplitude and φ the phase of thesamples. The sign "≃" arises from the fact that K'≃K and that the FFTreception circuit is offset.

If we examine the signal 1 packets later, i.e. the samples(n+1×1152+i+128, i=0, . . . 1023), then n→n+1×1152 and j→j+1 (we decodethe information from the (j+1)^(th) packet).

The FFT circuit 25 gives: ##EQU16##

If we compute φ'j+1, k-φ'j,k, we obtain: ##EQU17## therefore representsthe phase rotation due to the poor aligning of the local oscillators.

Nevertheless, in the transmission signal, there are two carriers ormaster lines, k₁ and k₂, such that φ_(j),k1 and φ_(j),k2 are constantwhatever the packet j. Moreover, these lines having continuous phase,that is to say free of phase jump. The analysis can be done anywherewithin the signal received, this being conveyed by the relationships:

    k1+D=n1×32 n, and n1εN

    k2+D=n2×32

In this case, the difference between the phases computed by the FFTcircuit for these two lines and for received data separated by 1152×1samples is given, on putting k₁,2 =k₁ or k₂, by: ##EQU18##

Expanding, we obtain: ##EQU19##

If we compute:

    R (δ.sub.1, δ.sub.2, δ.sub.3, 1, k.sub.1)-R (δ.sub.1, δ.sub.2, δ.sub.3, 1, k.sub.2)=Δ(δ.sub.1, 1)

We obtain: ##EQU20## hence proportional to δ₁

If for example k₁ >k₂, then:

    Δ(δ.sub.1, 1)<0→δ.sub.1 >0 we decrease f'.sub.e

    Δ(δ.sub.1, 1)>0→δ.sub.1 <0 we increase f'.sub.e

    Δ(δ.sub.1, 1)=0→δ.sub.1 =0 f'.sub.e properly aligned.

If we compute: ##EQU21## being a known constant which depends only onthe indices k₁ and k₂ of the carriers used as master lines. This knownnumber will therefore be coded over n bits (n depending on the accuracydesired) for installation in a D.S.P. (Digital Signal Processor).

We obtain ##EQU22##

We therefore see that by determining Δ(δ₁, 1) and Δ(δ₂, δ₃, 1), we canobtain values making it possible to alter the frequency of the samplingoscillator and the frequency of the intermediate frequency/basebandtranslation oscillator. ##EQU23## where for example φ'_(j),k1,2 is thephase term given by the FFT reception circuit 25 for the carrier k₁ ork₂ and for an arbitrary input sample block numbered j and whereφ'_(j+1),k1,k2 is then given for an input sample block separate from theblock No. j for 1152×1 samples;

Δ(δ₁, 1) and Δ(δ₂, δ₃, 1) can be obtained by carrying out the functionsrepresented in FIG. 3. In this FIG. 3, the FFT circuit 25 makes itpossible to obtain at output the value x'_(k1) and x'_(k2) correspondingto the carriers K₁ and K₂ respectively. Actually, the FFT circuit doesnot give the amplitude and phase of the carriers directly but thevalues:

    x'.sub.j,k1 =ρ'.sub.j,k1 e.sup.jφ' j,k1

    x'.sub.j,k2 =ρ'.sub.j,k2.sup.ejφ' j,k2

As represented in FIG. 3, the output x'_(k1) from the FFT circuit 25 issent respectively as input to a means 40 for producing a delay of 1samples and to the input of a divider 41 which receives, on its otherinput, the output from the means 40. The output from the divider 41 issent to a circuit 42 handling the imaginary part of the signal arisingfrom the divider 41. Indeed, if we regard the amplitude of the carriersas constant between two measurements, then: ##EQU24##

If the difference of the phases is small (→weak offset of the localoscillators) then we can write: ##EQU25## or else we use a PROM memorygiving the tabulation of the function as represented in FIG. 4 explainedbelow.

The output from the circuit 42 is sent to a low-pass 43. This is in facta circuit which carries out an averaging over several elements, that isto say which carries out a filtering of the information in order toeliminate the noise which is regarded as having zero mean. The outputfrom the circuit 43 is sent to a subtractor 44. Similarly, the signalx'_(k2) arising from the FFT circuit 25 is sent to a means 40' producinga digital delay of, for example, 1 packets of 1152 samples. The signalX'_(K2) is also sent to an input of a divider 41' which receives, on itsother input, the signal arising from the circuit 40' so as to carry outthe division: ##EQU26## as mentioned in the above formula. The outputfrom the divider 41' is sent to a circuit 42' extracting the imaginarypart. The output from the circuit 42' is sent to a low-pass filter 43'identical to the filter 43. The output from the filter 431 is sentrespectively as input to an adder 45 which receives on its other inputthe output from the filter 43 and to the second input of the subtractor44 which outputs the value Δ(δ₁, 1). Furthermore, the output from thesubtractor 44 is sent to a circuit 46 so as to multiply the outputelement by a coefficient ##EQU27## which is known and quantised over anumber of bits sufficient to ensure good accuracy.

The output from the circuit 46 is sent to one of the inputs of asubtractor 47 which receives on its other input the output from theadder 45. The output from the subtractor gives the value Δ(δ₂, δ₃, 1).Furthermore, the two values Δ(δ₁, 1) and Δ(δ₂, δ₃, 1) are used to carryout the realignment of the frequency of the local oscillator 222 and alocal sampling oscillator (not shown) for sampling the ADC converter 23.Moreover, the two values Δ(δ₁, 1) and Δ(δ₂, δ₃, 1) are also input to acircuit 48 for control of the analysis time. The outputs from theanalysis time control circuit are sent to the circuits 40 and 40' inorder to modify the value of 1, that is to say the value of the digitaldelay measured as number of packets of 1152 samples and to the circuits43 and 43'. Actually, when approaching ideal values for the localoscillators, the terms Δ(δ₁, 1) and Δ(δ₂, δ₃, 1) tend to become smallerand smaller, except if at the same time we increase the value of 1, thatis to say the analysis time to permit the phases to rotate. This is theobjective of the circuit for control of the analysis time.

In FIG. 4 has been represented another way of obtaining the termsΔ(δ₁, 1) and Δ(δ₂, δ₃, 1). This manner can be used without making anyapproximation regarding the phase difference. In FIG. 4, the sameelements as those of FIG. 3 carry the same references and will not beredescribed in detail. In this figure, the dividers 41 and 41' and thecircuits 42 and 42' handling the imaginary part have been replaced by aPROM memory 50 carrying out a cartesian-polar transformation making itpossible to obtain ρ'_(j),k1, ρ'_(j),k2, and φ'_(j),k1, φ'_(j),k2, andby two subtractors 51 and 51'.

It is clear to the expert that FIGS. 3 and 4 are given merely by way ofexample.

We claim:
 1. Method of realigning the oscillators of a receivercomprising a high frequency/intermediate frequency translationoscillator, an intermediate frequency/baseband translation oscillator,and a sampling oscillator receiving a signal modulated according tomulticarrier modulation of OFDM (Orthogonal Frequency DivisionMultiplexing) type using inverse fast Fourier transform FFT⁻¹computation the spectrum of the said signal comprising two masterspectral lines having a fixed frequency difference between them, themethod comprising computation of the variation of the phase of the twospectral lines as a function of time with the aid of fast Fouriertransform on reception, then said oscillators being frequency adjustableand setting the frequency of the sampling oscillator and the frequencyof at least one of the other two oscillators according to the result ofsaid computations.
 2. Method according to claim 1, characterised in thatthe modification of the frequency of the intermediate frequency/basebandtranslation oscillator is carried out by computing: ##EQU28## in whichφ'_(j),k1 and φ'_(j),k2 are respectively the phase given by the fastFourier transform computation on reception for the carriers k₁ and k₂for an input sample block j and φ'_(j+1),k1 and φ'_(j+1),k2 being thephase for a block separated from the block j by q×1 samples, and

    Δ(δ.sub.1, 1)=[φ'.sub.j+1,k1 -φ'.sub.j,k1 ]-[φ'.sub.j+1, k2 -φ'.sub.j,k2 ]

and by modifying the frequency as a function of the value of Δ(δ₂, δ₃,1), where Δ(δ₂, δ₃, 1) is a phase difference corresponding to thefrequency offset δ₂, δ₃ seen 1 packets later, the oscillator beingcorrectly adjusted when:

    Δ(δ.sub.2, δ.sub.3, 1)=0.


3. Method according to claim 1, characterised in that the modificationof the frequency of the oscillator giving the sampling frequency iscarried out by computing:

    Δ(δ.sub.1, 1)=[φ'.sub.j+1,k1 -φ'.sub.j,k1 ]-[φ'.sub.j+1, k2 -φ'.sub.j,k2 ]

and by modifying the frequency as a function of the value of Δ(δ₁,1),the oscillator being correctly adjusted when Δ(δ₁,1)=0.
 4. Device forimplementing the method according to any one of claims 1 to 3,characterised in that it comprises an FFT circuit (25) providing at itsoutput:means (40, 40') for delaying by q×1 samples the values X'_(k1),and X'_(k2) arising from the FFT circuit (25) and corresponding to themaster lines k₁ and k₂, two dividers (41, 41') carrying out respectivelythe division ##EQU29## two means (42, 42') for the imaginary part of thevalues arising from each divider, a subtractor (44) subtracting thevalue arising from one of the means handling the imaginary part from thevalue arising from the other means handling the imaginary part so as toobtain Δ(δ₁,1), an adder (45) adding the values arising from the twomeans (42, 42') for the imaginary part, a multiplier multiplying thevalue Δ(δ, ₁ 1) by a coefficient ##EQU30## a subtractor (47) subtractingthe value arising from the multiplier from the value arising from theadder so as to obtain Δ(δ₂, δ₃, 1).
 5. Device according to claim 4,characterised in that it includes at the output of each means for theimaginary part, an averaging device (43, 43').
 6. Device according toclaim 4, characterized in that it additionally includes an analysis timecontrol circuit (48) allowing modification of the analysis time, namelythe value of
 1. 7. Device according to claim 5, characterised in thatthe dividers and the means for the imaginary part of the values arisingfrom each divider comprise an angular PROM memory performing thecartesian-polar transformation and by two subtractors.
 8. Deviceaccording to claim 5, characterized in that it additionally includes ananalysis time control circuit (48) allowing modification of the analysistime, namely the value of 1.